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NOTE: The fields listed on this page cover possible configurations. Some fields may not be present on your system. |
If the processor is capable of a particular function/property, this field displays True, otherwise False.
If a particular function/property of a processor is enabled, this field displays True, otherwise False. If a function cannot be enabled or disabled by user, Not Applicable is displayed.
64-bit Support | Supports 64-bit. |
Hyperthreading (HT) | Intel's implementation of the simultaneous multithreading technology. |
Virtualization Technology (VT) | Intel's virtualization extension to the 64-bit x86 architecture. |
Demand Based Switching (DBS) | A power-management technology developed by Intel in which the applied voltage and clock speed for a microprocessor are kept to the minimum necessary to allow optimum performance of required operations. |
Execute Disable (XD) | Allows properly-written applications to mark off memory space as executable, so that code trying to access space above and beyond that will not be executed. |
64-bit Support | Supports 64-bit. |
AMD PowerNow!™ | A processor feature that enables dynamically adjusting performance based on CPU utilization – helping systems to run at optimum performance and power levels, reducing electricity costs. |
AMD-V™ | AMD's virtualization extension to the 64-bit x86 architecture. |
No Execute (NX) | Allows properly-written applications to mark off memory space as executable, so that code trying to access space above and beyond that will not be executed. |
Use this window to view cache information for each cache present on the microprocessor.
Cache is small high-speed memory that contains the most recently accessed pieces of main memory. The cache keeps a copy of data or instructions from main memory for quicker retrieval. Cache decreases the amount of time it takes to move data from main memory to the processor and back again. The processor cache is faster than the system's main RAM.
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NOTE: Some cache devices are internal to the processors on
which they reside. When the cache is internal to a processor, the following fields and
their values do not appear in the Cache Information for Processor on Connector n
window:
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The following fields are defined for a cache device on a particular processor. Some fields do not appear if the cache is internal to the processor.
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NOTE: This help page may include information about cache features that are not supported by your system. Server Administrator only displays the cache features that are supported on your system. |
Status | Indicates whether the cache on the processor is enabled or disabled. |
Level | Displays the cache level. Primary level cache (L1) is a very fast memory bank located near the processor execution units. Secondary level cache (L2) is a larger staging area that feeds the primary cache. Tertiary level cache (L3), if available, is an additional, larger memory bank which feeds data to the secondary cache. All of these cache levels are located in the processor. |
Speed | Indicates the rate that the cache can forward data from main memory to the processor. |
Max Size | Displays the maximum memory that the cache can occupy in KB. |
Installed Size | Displays the actual size of the cache. |
Type | Indicates whether the cache type is Data or Unified. |
Location | Indicates whether the cache is located on the processor or on a chip set outside the processor. |
Write Policy | Describes how the cache deals with a write
cycle. In a Write-Back policy, the cache acts like a buffer. When the processor starts a write cycle, the cache receives the data and stops the cycle. The cache then writes the data back to main memory when the system bus is available. In a Write-Through policy, the processor writes through the cache to main memory. The write cycle does not complete until the data is stored into main memory. If the write policy specifies Varies with Address, then the policy is either write-back or write-through, according to the memory address. |
Associativity | Fully Associative cache allows any line
in main memory to be stored at any location in the cache. 8-Way Set-Associative cache directly maps eight specific lines of memory to the same eight lines of cache. 4-Way Set-Associative cache directly maps four specific lines of memory to the same four lines of cache. 3-Way Set-Associative cache directly maps three specific lines of memory to the same three lines of cache. 2-Way Set-Associative cache directly maps two specific lines of memory to the same two lines of cache. 1-Way Set-Associative cache directly maps a specific line of memory in the same line of cache. For example, Line 0 of any page in memory must be stored in Line 0 of cache memory. |
Cache Device Supported Type | Indicates the type of static random access memory (SRAM) that the device can support. |
Cache Device Current Type | Indicates the type of the currently installed SRAM that the cache is supporting. |
External Socket Name | Silk-screen name printed on the system board next to the socket. |
Error Correction Type | Identifies the type of error checking and correction (ECC) that this memory can perform. For example, single-bit ECC or multibit ECC. |
Prints a copy of the open window to your default printer. |
Export | Saves a text file containing the contents of this window (the values of each data field separated by a customizable delimiter) to a destination you specify. |
E-mails the contents of this window to your designated recipient. See the Server Administrator User's Guide for instructions about configuring your Simple Mail Transfer Protocol (SMTP) server. | |
Refresh | Updates the screen with latest information. |